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Computer Engineering

Digital Design

Combine theory, Verilog, and laboratory experiments to design and analyze digital circuits.

Instructor Dr. Waleed A. Yousef Adjunct Professor, University of Victoria, Canada
A digital integrated circuit and precisely routed copper connections

01

Course overview

Combine theory, Verilog, and laboratory experiments to design and analyze digital circuits.

02

What you will learn

This course combines three approaches to teach students Digital Design, which is a fundamental prerequisite for understanding computer design and architecture. Firstly, and most importantly, theoretical aspects of the subject will be covered in lectures, along with exercises in sections. By the end of the course, students should be capable of designing, analyzing, and implementing combinational and synchronous digital circuits.

A second objective is to teach students digital design using a Hardware Description Language (HDL). By the end of the semester, students will be able to analyze logic circuits using Verilog, one of the available HDLs.

A third objective is to develop the practical skills of the students through laboratory experiments. Students will have the opportunity to implement logic circuits using breadboards and ICs. If time permits, an introduction to Field Programmable Gate Arrays (FPGAs) technology will be provided.

A fast introduction (covering a few sections from Chapter 1) will be offered, followed by a detailed study of Chapters 2-7, with only a few sections skipped. At the end of each chapter, Verilog code for some circuits will be explained. If time permits, Chapter 8 will be fully or partially covered. Additionally, if time permits, an introduction to FPGA technology will be given.

03

Lecture syllabus

Video titles and durations as published on Arabsera. The advertised lecture total may differ from the number of video entries, which can include introductions, tutorials, and split sessions.

Video titles and durations 26
  1. 01 Introduction to Digital Design: from mathematical logic to logic circuits
  2. 02-a Boolean Algebra and Logic Gates
  3. 02-b Boolean Algebra and Logic Gates
  4. 02-c Boolean Algebra and Logic Gates
  5. 03-a Gate-Level Minimization: K-Map
  6. 03-b Gate-Level Minimization: cont.
  7. 03-c Gate-Level Minimization: Verilog
  8. 04-a Combinational Logic: adders
  9. 04-b Combinational Logic: adders 2
  10. 04-c Combinational Logic: multipliers and comparators
  11. 04-d Combinational Logic: decoders & encoders
  12. 04-e Combinational Logic: multiplexers
  13. 05-a Synchronous Sequential Logic: latches & flip-flops
  14. 05-b Synchronous Sequential Logic: analysis
  15. 05-c Synchronous Sequential Logic: design 0
  16. 05-d Synchronous Sequential Logic: design 1
  17. 05-e Synchronous Sequential Logic: design 2
  18. 06-a Registers and Counters: load/up/down
  19. 06-b Serial Registers
  20. 06-c Serial Adders
  21. 06-d Universal Register and Ripple Counter
  22. 06-e BCD Ripple Counter and Other Counters
  23. 07-a Memory: RAM
  24. 07-b Memory: ROM
  25. 08-a Register Transfer Language (RTL)
  26. 08-a-cont. RTL and Computer Organization

04

Teaching support (check your plan)

  • Discussion groups
  • TA-human texting for Q&A
  • TA-GPT (coming soon)

05

Textbook

Mano, M. M., and Ciletti, M. D. (2007). Digital Design (4th ed.)

06

Certificate

Awarded after passing a brief sample exam, which you may attempt multiple times.